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| 160 MHz Rail-to-Rail Amplifier with Disable AD8041* FEATURES Fully Specified for +3 V, +5 V, and 5 V Supplies Output Swings Rail to Rail Input Voltage Range Extends 200 mV Below Ground No Phase Reversal with Inputs 1 V Beyond Supplies Disable/Power-Down Capability Low Power of 5.2 mA (26 mW on 5 V) High Speed and Fast Settling on 5 V: 160 MHz -3 dB Bandwidth (G = +1) 160 V/ s Slew Rate 30 ns Settling Time to 0.1% Good Video Specifications (RL = 150 , G = +2) Gain Flatness of 0.1 dB to 30 MHz 0.03% Differential Gain Error 0.03 Differential Phase Error Low Distortion -69 dBc Worst Harmonic @ 10 MHz Outstanding Load Drive Capability Drives 50 mA 0.5 V from Supply Rails Cap Load Drive of 45 pF APPLICATIONS Power Sensitive High Speed Systems Video Switchers Distribution Amplifiers A/D Drivers Professional Cameras CCD Imaging Systems Ultrasound Equipment (Multichannel) Single-Supply Multiplexer PRODUCT DESCRIPTION CONNECTION DIAGRAM 8-Lead PDIP, CERDIP and SOIC NC 1 -INPUT 2 INPUT 3 -VS 4 8 DISABLE 7 VS 6 OUTPUT AD8041 (Top View) 5 NC NC = NO CONNECT The output voltage swing extends to within 50 mV of each rail, providing the maximum output dynamic range. Additionally, it features gain flatness of 0.1 dB to 30 MHz while offering differential gain and phase error of 0.03% and 0.03 on a single 5 V supply. This makes the AD8041 ideal for professional video electronics such as cameras, video switchers, or any high speed portable equipment. The AD8041's low distortion and fast settling make it ideal for buffering high speed A-to-D converters. The AD8041 has a high speed disable feature useful for multiplexing or for reducing power consumption (1.5 mA). The disable logic interface is compatible with CMOS or opencollector logic. The AD8041 offers a low power supply current of 5.8 mA maximum and can run on a single 3 V power supply. These features are ideally suited for portable and batterypowered applications where size and power are critical. The wide bandwidth of 160 MHz along with 160 V/s of slew rate on a single 5 V supply make the AD8041 useful in many general-purpose high speed applications where dual power supplies of up to 6 V and single supplies from 3 V to 12 V are needed. The AD8041 is available in 8-lead PDIP and SOIC over the industrial temperature range of -40C to +85C. 2 1 0 VS = 5V G = +2 RF = 400 The AD8041 is a low power voltage feedback, high speed amplifier designed to operate on +3 V, +5 V, or 5 V supplies. It has true single-supply capability with an input voltage range extending 200 mV below the negative rail and within 1 V of the positive rail. 5V NORMALIZED GAIN (dB) 1V 200ns -1 -2 -3 -4 -5 -6 -7 2.5V 0V -8 0 20 40 60 FREQUENCY (MHz) 80 100 Figure 1. Output Swing: G = -1, VS = 5 V *Protected by U.S.Patent No. 5,537,079. Figure 2. Frequency Response: G = +2, VS = 5 V REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD8041-SPECIFICATIONS (@ T = 25 C, V = 5 V, R = 2 k A S L to 2.5 V, unless otherwise noted.) AD8041A Typ 160 30 160 24 35 55 -72 16 600 0.03 0.01 0.03 0.19 2 7 8 3.2 3.5 0.5 Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 0.1% Settling Time to 0.01% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC) Differential Phase Error (NTSC) DC PERFORMANCE Input Offset Voltage Conditions G = +1 G = +2, RL = 150 G = -1, VO = 2 V Step VO = 2 V p-p G = -1, VO = 2 V Step Min 130 130 Max Unit MHz MHz V/s MHz ns ns dB nV/Hz fA/Hz % % Degrees Degrees mV mV V/C A A A dB dB k pF V dB V V V mA mA mA pF fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 k f = 10 kHz f = 10 kHz G = +2, RL = 150 to 2.5 V G = +2, RL = 75 to 2.5 V G = +2, RL = 150 to 2.5 V G = +2, RL = 75 to 2.5 V TMIN to TMAX Offset Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing: RL = 10 k Output Voltage Swing: RL = 1 k Output Voltage Swing: RL = 50 Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Disabled) Power Supply Rejection Ratio DISABLE CHARACTERISTICS Turn-Off Time Turn-On Time Off Isolation (Pin 8 Tied to -VS) Off Voltage (Device Disabled) On Voltage (Device Enabled) Specifications subject to change without notice. 10 1.2 0.2 95 90 160 1.8 -0.2 to +4 80 0.05 to 4.95 0.1 to 4.9 0.3 to 4.5 50 90 150 45 RL = 1 k TMIN to TMAX 86 VCM = 0 V to 3.5 V 74 0.35 to 4.75 0.4 to 4.4 VOUT = 0.5 V to 4.5 V Sourcing Sinking G = +1 3 5.2 1.4 80 120 230 70 VS = 0, +5 V, 1 V VO = 2 V p-p @ 10 MHz, G = +2 RF = RL = 2 k RF = RL = 2 k RL = 100 , f = 5 MHz, G = +2, RF = 1 k 72 V mA mA dB ns ns dB V V -2- REV. B AD8041 SPECIFICATIONS (@ T = 25 C, V = 3 V, R = 2 k A S L to 1.5 V, unless otherwise noted.) Min 120 120 AD8041A Typ 150 25 150 20 40 55 -55 16 600 0.07 0.05 2 7 8 3.2 3.5 0.6 Max Unit MHz MHz V/s MHz ns ns dB nV/Hz fA/Hz % Degrees mV mV V/C A A A dB dB k pF V dB V V V mA mA mA pF 12 5.6 1.5 V mA mA dB ns ns dB V V Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 0.1% Settling Time to 0.01% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC) Differential Phase Error (NTSC) DC PERFORMANCE Input Offset Voltage Conditions G = +1 G = +2, RL = 150 G = -1, VO = 2 V Step VO = 2 V p-p G = -1, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, G = -1, RL = 100 f = 10 kHz f = 10 kHz G = +2, RL = 150 to 1.5 V, Input VCM = 1 V G = +2, RL = 150 to 1.5 V, Input VCM = 1 V TMIN to TMAX Offset Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing: RL = 10 k Output Voltage Swing: RL = 1 k Output Voltage Swing: RL = 50 Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Disabled) Power Supply Rejection Ratio DISABLE CHARACTERISTICS Turn-Off Time Turn-On Time Off Isolation (Pin 8 Tied to -VS) Off Voltage (Device Disabled) On Voltage (Device Enabled) Specifications subject to change without notice. 10 1.2 0.2 94 89 160 1.8 -0.2 to +2 80 0.05 to 2.95 0.1 to 2.9 0.25 to 2.75 50 70 120 40 RL = 1 k TMIN to TMAX 85 VCM = 0 V to 1.5 V 72 0.45 to 2.7 0.5 to 2.6 VOUT = 0.5 V to 2.5 V Sourcing Sinking G = +1 3 VS = 0, +3 V, 0.5 V VO = 2 V p-p @ 10 MHz, G = +2 RF = RL = 2 k RF = RL = 2 k RL = 100 , f = 5 MHz, G = +2, RF = 1 k 68 5.0 1.3 80 90 170 70 -3- AD8041 SPECIFICATIONS Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 0.1% Settling Time to 0.01% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC) Differential Phase Error (NTSC) DC PERFORMANCE Input Offset Voltage TMIN to TMAX Offset Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing: RL = 10 k Output Voltage Swing: RL = 1 k Output Voltage Swing: RL = 50 Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Disabled) Power Supply Rejection Ratio DISABLE CHARACTERISTICS Turn-Off Time Turn-On Time Off Isolation (Pin 8 Tied to -VS) Off Voltage (Device Disabled) On Voltage (Device Enabled) Specifications subject to change without notice. (@ TA = 25 C, VS = 5 V, RL = 2 k Conditions to 0 V, unless otherwise noted.) AD8041A Typ 170 32 170 26 30 50 -77 16 600 0.02 0.02 0.03 0.10 2 10 1.2 0.2 99 95 160 1.8 -5.2 to +4 80 -4.95 to +4.95 -4.8 to +4.8 -4.5 to +3.8 50 100 160 50 12 6.5 2.2 7 8 3.2 3.5 0.6 Min 140 140 Max Unit MHz MHz V/s MHz ns ns dB nV/Hz fA/Hz % % Degrees Degrees mV mV V/C A A A dB dB k pF V dB V V V mA mA mA pF V mA mA dB ns ns dB V V G = +1 G = +2, RL = 150 G = -1, VO = 2 V Step VO = 2 V p-p G = -1, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 k f = 10 kHz f = 10 kHz G = +2, RL = 150 G = +2, RL = 75 G = +2, RL = 150 G = +2, RL = 75 RL = 1 k TMIN to TMAX 90 VCM = -5 V to +3.5 V 72 -4.45 to +4.6 -4.3 to +3.2 VOUT = -4.5 V to +4.5 V Sourcing Sinking G = +1 3 VS = -5 V, +5 V, 1 V VO = 2 V p-p @ 10 MHz, G = +2 RF = 2 k RF = 2 k RL = 100 , f = 5 MHz, G = +2, RF = 1 k 68 5.8 1.6 80 120 320 70 REV. B AD8041 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION (W) Supply Voltage ............................................................ 12.6 V Internal Power Dissipation2 PDIP Package (N) .................................................... 1.3 W SOIC Package (R) .................................................... 0.9 W Input Voltage (Common Mode) ...................................... VS Differential Input Voltage ........................................... 3.4 V Output Short-Circuit Duration .......................................... Observe Power Derating Curves Storage Temperature Range N, R .............. -65C to +125C Operating Temperature Range (A Grade) ... -40C to +85C Lead Temperature Range (Soldering 10 sec) ............... 300C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for the device in free air: 8-Lead PDIP Package: JA = 90C/W. 8-Lead SOIC Package: JA = 155C/W. the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. While the AD8041 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. 2.0 8-LEAD PDIP PACKAGE TJ = 150 C 1.5 1.0 8-LEAD SOIC PACKAGE 0.5 MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8041 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE ( C) Figure 3. Maximum Power Dissipation vs. Temperature ORDERING GUIDE Model AD8041AN AD8041AR AD8041AR-REEL AD8041AR-REEL7 AD8041ARZ-REEL1 5962-9683901MPA2 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C Package Description 8-Lead PDIP 8-Lead Plastic SOIC 13" Tape and Reel 7" Tape and Reel 13" Tape and Reel 8-Lead CERDIP Package Options N-8 R-8 R-8 R-8 R-8 Q-8 NOTES 1 The Z indicates a lead-free product. 2 Refer to official DSCC drawing for tested specifications. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8041 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B -5- AD8041-Typical Performance Characteristics 30 VS = 2.5V TA = 25 C 91 PARTS MEAN = +0.21 STD DEVIATION = 1.47 100 25 NUMBER OF PARTS IN BIN 95 OPEN-LOOP GAIN (dB) 20 90 15 85 VS = 5V TA = 25 C 10 80 5 75 0 70 -6 -5 -4 -3 -2 -1 0 1 VOS (mV) 2 3 4 5 6 0 250 500 750 1000 1250 1500 LOAD RESISTANCE ( ) 1750 2000 TPC 1. Typical Distribution of VOS TPC 4. Open-Loop Gain vs. RL to 25C 0.20 MEAN = 0.02 V/ C STD DEV = 2.87 V/ C SAMPLE SIZE = 45 100 97 OPEN-LOOP GAIN (dB) PROBABILITY DENSITY 0.15 94 VS = 5V RL = 1k 91 TO 2.5V 0.10 0.05 88 0 -10 -7.5 -5 -2.5 0 2.5 VOS DRIFT ( V/ C) 5 7.5 10 85 -60 -40 -20 0 20 40 60 80 TEMPERATURE ( C) 100 120 TPC 2. VOS Drift Over -40C to +85C TPC 5. Open-Loop Gain vs. Temperature 2 VS = 5V VCM = 0V INPUT BIAS CURRENT ( A) 100 RL = 500 90 OPEN-LOOP GAIN (dB) TO 2.5V VS = 5V 1.5 80 RL = 50 TO 2.5V 1 70 60 0.5 50 0 -45 -35 -25 -15 -5 5 15 25 35 45 TEMPERATURE ( C) 55 65 75 85 40 0 0.5 1 1.5 2 2.5 3 3.5 OUTPUT VOLTAGE (V) 4 4.5 5 TPC 3. IB vs. Temperature TPC 6. Open-Loop Gain vs. Output Voltage -6- REV. B AD8041 200 DIFF GAIN (%) INPUT VOLTAAGE NOISE (nV/ Hz) 150 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0.000 -0.005 -0.010 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0.000 -0.005 -0.010 VS = 5V G = +2 RL = 150 TO 2.5V VS = 5V G = +2 RL = 150 DIFF PHASE (Degrees) 100 1st 2nd 3rd VS = 5V G = +2 RL = 150 4th 5th 6th 7th 8th 9th 10th 11th TO 2.5V VS = 5V G = +2 RL = 150 50 0 10 100 1k FREQUENCY (Hz) 10k 100k 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th DC OUTPUT LEVEL (100 IRE MAX) TPC 7. Input Voltage Noise vs. Frequency TPC 10. Differential Gain and Phase Errors -30 TOTAL HARMONIC DISTORTION (dBc) 6.5 VS = 3V, AV = -1, RL = 100 TO 1.5V CLOSED-LOOP GAIN (dB) VS = 5V, AV = 2, RL = 100 TO 2.5V 6.4 6.3 6.2 6.1 6.0 32.4MHz 5.9 5.8 5.7 5.6 5.5 8 9 10 1 100 10 FREQUENCY (MHz) 500 VS = 5V G = +2 RL = 150 RF = 402 -40 -50 -60 -70 -80 -90 TO 2.5V VS = 5V, AV = 1, RL = 100 TO 2.5V VS = 5V, AV = 2, RL = 1k TO 2.5V VS = 5V, AV = 1, RL = 1k TO 2.5V 2 3 4 5 67 FUNDAMENTAL FREQUENCY (MHz) -100 1 TPC 8. Total Harmonic Distortion TPC 11. 0.1 dB Gain Flatness -30 10MHz -40 -50 WORST HARMONIC (dBc) 90 80 70 GAIN 60 50 40 30 20 10 0 PHASE VS = 5V RL = 2k TO 2.5V CL = 5pF TO 2.5V 450 360 270 180 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 0.5 1 2.5 1.5 2 3 3.5 OUTPUT VOLTAGE (VP-P) 4 4.5 5 VS = 5V RL = 2k G = +2 TO 2.5V 1MHz OPEN-LOOP GAIN (dB) 5MHz 0 -90 -180 -270 -360 -450 500 -10 0.01 0.1 10 FREQUENCY (MHz) 100 TPC 9. Worst Harmonic vs. Output Voltage TPC 12. Open-Loop Gain and Phase vs. Frequency REV. B -7- PHASE ( C) 90 AD8041 5 4 3 VS = 5V RL = 2k TO 2.5V CL = 5pF G = +1 T = +125 C 40 T = +25 C TIME (ns) 50 G = -1 VS = 3V, 0.1% CLOSED-LOOP GAIN (dB) 2 1 0 -1 -2 VS = 30 5V, 0.1% T = -55 C VS = 3V, 1% 20 -3 -4 -5 1 10 100 FREQUENCY (MHz) 500 10 0.5 1 VS = 1.5 INPUT STEP (V p-p) 5V, 1% 2 TPC 13. Closed-Loop Frequency Response vs. Temperature TPC 16. Settling Time vs. Input Step 5 4 3 CLOSED-LOOP GAIN (dB) -10 G = +1 RL = 2k CL = 5pF VS = 3V RL AND CL TO 1.5V VS = 5V RL AND CL TO 2.5V CMRR (dB) -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0.01 0.1 1 10 FREQUENCY (MHz) 100 500 VS = +3V AND 5V 2 1 0 VS = -1 -2 -3 -4 -5 1 5V 10 100 FREQUENCY (MHz) 500 TPC 14. Closed-Loop Frequency Response vs. Supply TPC 17. CMRR vs. Frequency 1000 OUTPUT SATURATION VOLTAGE (mV) 100 G = +1 VS = 5V 10 VS = 5V 12 5 C OUTPUT RESISTANCE ( ) 100 V +5 - VO H ,+ 1 5C , -5 V OH - C +5V +125 VOL, 0.1 10 55 C V OL, - 0.01 0.01 0.1 1 10 FREQUENCY (MHz) 100 500 0 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 10 0 TPC 15. Output Resistance vs. Frequency TPC 18. Output Saturation Voltage vs. Load Current -8- REV. B AD8041 8 90 100k 80 1k VS = 5V RSERIES CLOAD VIN 60 50 40 30 20 20 PHASE MARGIN 45 PHASE MARGIN 7 70 SUPPLY CURRENT (mA) 6 VS = 5V VS = 5V 5 VS = 3V 4 3 CAPACITIVE LOAD (pF) 10 2 -60 -40 -20 0 20 40 60 TEMPERATURE ( C) 80 100 120 0 0 10 20 30 40 SERIES RESISTANCE ( ) 50 60 TPC 19. Supply Current vs. Temperature TPC 22. Capacitive Load vs. Series Resistance 40 20 VS = 5V 5 4 NORMALIZED OUTPUT (dB) 0 -20 -PSRR 3 G = +2 2 1 0 -1 -2 G = +10 -3 -4 G = +5 VS = 5V RL = 5k RF = 2k TO 2.5V PSRR (dB) -40 -60 +PSRR -80 -100 -120 -140 -160 0.01 0.1 1 10 FREQUENCY (MHz) 100 500 G = +2, RF = 402 -5 1 10 100 FREQUENCY (MHz) 500 TPC 20. PSRR vs. Frequency TPC 23. Frequency Response vs. Closed-Loop Gain 10 9 8 7 VS = 5V RL = 2k 1.600V 1.575V 1.550V 1.525V 1.500V 1.475V 1.450V 1.425V 50mV 1.400V 10ns VIN = 0.1V p-p RL = 2k VS = 3V G = +1 VOUT p-p (V) 6 5 4 3 2 1 0 0.1 1 10 FREQUENCY (MHz) 100 1000 TPC 21. Output Voltage Swing vs. Frequency TPC 24. Pulse Response, VS = 3 V REV. B -9- AD8041 5V 4.840V MAX 2.60V VS = 5V G = +1 RL = 2k VL = 5pF 4V RL = 150 TO 2.5V 2.55V 3V 2.50V 2V 2.45V 1V 0.111V MIN 1V 0V 200 s 2.40V 50mV 40ns a. TPC 27. 100 mV Step Response, VS = 5 V, G = +1 5V 4.741V MAX 4V RL = 150 3V TO GND 3.0V VIN = 3V p-p f = 0.1MHz RL = 2k VS = 3V G = -1 2.5V 2.0V 1.5V 2V 1.0V 1V 1V 0V 0.043V MIN 200 s 0V 0.5V 500mV 2s b. TPC 25. Output Swing vs. Load Reference Voltage, VS = 5 V, G = -1 TPC 28. Output Swing, VS = 3 V, VIN = 3 V p-p 4.5V VS = 5V G = +2 RL = 2k VIN = 1V p-p 3.0V VIN = 2.8V p-p f = 0.8MHz RL = 2k VS = 3V G = -1 2.5V 3.5V 2.0V 2.5V 1.5V 1.0V 1.5V 0.5V 1V 0.5V 40ns 500mV 0V 2s TPC 26. One Volt Step Response, VS = 5 V, G = +2 TPC 29. Output Swing, VS = 3 V, VIN = 2.8 V p-p -10- REV. B AD8041 Overdrive Recovery Overdrive of an amplifier occurs when the output and/or input range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure 4, the AD8041 recovers within 50 ns from negative overdrive and within 25 ns from positive overdrive. Capacitor C9. R1 is the output resistance of the input stage; gm is the input transconductance. C7 and C9 provide Miller compensation for the overall op amp. The unity gain frequency will occur at gm/C9. Solving the node equations for this circuit yields: VOUT Vi = A0 g ( sR1 [C 9 ( A2 + 1)] + 1) x s m2 + 1 C3 5.0V OUTPUT INPUT 2.5V G = +2 VS = 5V where A0 = gmgm2 R2 R1 A2 = gm2 R2 (Open-Loop Gain of Op Amp) (Open-Loop Gain of Output Stage) 0V 50mV 40ns Figure 4. Overdrive Recovery Circuit Description The first pole in the denominator is the dominant pole of the amplifier and occurs at about 180 Hz. This equals the input stage output impedance R1 multiplied by the Miller-multiplied value of C9. The second pole occurs at the unity-gain bandwidth of the output stage, which is 250 MHz. This type of architecture allows more open-loop gain and output drive to be obtained than a standard two-stage architecture would allow. Output Impedance The AD8041 is fabricated on Analog Devices' proprietary eXtra-Fast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar fT in the 2 GHz to 4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. These features allow the construction of high frequency, low distortion amplifiers with low supply currents. This design uses a differential output input stage to maximize bandwidth and headroom (see Figure 5). The smaller signal swings required on the first stage outputs (nodes S1P, S1N) reduce the effect of nonlinear currents due to junction capacitances and improve the distortion performance. With this design harmonic distortion of better than -85 dB @ 1 MHz into 100 with VOUT = 2 V p-p (Gain = +2) on a single 5 V supply is achieved. The complementary common-emitter design of the output stage provides excellent load drive without the need for emitter followers, thereby improving the output range of the device considerably with respect to conventional op amps. High output drive capability is provided by injecting all output stage predriver currents directly into the bases of the output devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by I8 and I5, along with a common-mode feedback loop (not shown). This circuit topology allows the AD8041 to drive 50 mA of output current with the outputs within 0.5 V of the supply rails. On the input side, the device can handle voltages from -0.2 V below the negative rail to within 1.2 V of the positive rail. Exceeding these values will not cause phase reversal; however, the input ESD devices will begin to conduct if the input voltages exceed the rails by greater than 0.5 V. A "Nested Integrator" topology is used in the AD8041 (see the small-signal schematic in Figure 6). The output stage can be modeled as an ideal op amp with a single-pole response and a unity-gain frequency set by transconductance gm2 and The low frequency open-loop output impedance of the common emitter output stage used in this design is approximately 6.5 k. While this is significantly higher than a typical emitter follower output stage, when connected with feedback, the output impedance is reduced by the open-loop gain of the op amp. With 110 dB of open-loop gain, the output impedance is reduced to less than 0.1 . At higher frequencies, the output impedance will rise as the open-loop gain of the op amp drops; however, the output also becomes capacitive due to the integrator capacitors C9 and C3. This prevents the output impedance from ever becoming excessively high (see TPC 15), which can cause stability problems when driving capacitive loads. In fact, the AD8041 has excellent cap-load drive capability for a high frequency op amp. TPC 22 demonstrates that the AD8041exhibits a 45 margin while driving a 20 pF direct capacitive load. In addition, running the part at higher gains will also improve the capacitive load drive capability of the op amp. VCC I1 R26 Q4 Q40 R15 R2 VEE VINP VINN S1P Q2 Q3 C7 VEE R5 R21 R3 S1N Q11 Q24 I7 Q47 I8 VCC Q13 Q17 Q22 Q7 Q21 Q27 C9 R23 R27 Q31 C3 VOUT I10 R39 Q5 I2 I3 Q25 Q51 Q50 Q39 Q23 VEE I9 Q36 I5 Q8 Figure 5. AD8041 Simplified Schematic REV. B -11- AD8041 C9 VS = 5V S1N C3 gmVi R1 gm2 S1P 10 100 90 R2 VOUT gmVi R1 C7 0% 1V 200ns Figure 6. Small Signal Schematic Disable Operation Figure 8. 2:1 Multiplexer Performance Single-Supply A/D Conversion The AD8041 has an active-low disable pin, which can be used to three-state the output of the part and also lower its supply current. If the disable pin is left floating, the part is enabled and will perform normally. If the disable pin is pulled to 2.5 V (min) below the positive supply, output of the AD8041 will be disabled and the nominal supply current will drop to less than 1.6 mA. For best isolation, the disable pin should be pulled to as low a voltage as possible; ideally, the negative supply rail. The disable pin on the AD8041 allows it to be configured as a 2:1 mux as shown in Figure 7 and can be used to switch many types of high speed signals. Higher order multiplexers can also be built. The break-before-make switching time is approximately 50 ns to disable the output and 300 ns to enable the output. 5V 10 F Figure 9 shows the AD8041 driving the analog inputs of the AD9050 in a dc-coupled system with single-ended signals. All components are powered from a single 5 V supply. The AD820 is used to offset the ground referenced input signal to the level required by the AD9050. The AD8041 is used to add in the offset with the ground referenced input signal and buffer the input to AD9050. The nominal input range of the AD9050 is 2.8 V and 3.8 V (1 V p-p centered at 3.3 V). This circuit provides 40 MSPS analog-to-digital conversion on just 330 mW of power while delivering 10-bit performance. 1k 5V VIN -0.5V TO +0.5V 1k 5V 10 2.8V - 3.8V 9 AD8041 AD9050 CH0 5MHz 3 50 2 330 7 0.1 F 6 4 5V 1k 3.3V AD8041 8 G = +2 330 1k AD820 0.1 F 50 5V 10 F Figure 9. 10-Bit, 40 MSPS A/D Conversion CH1 10MHz 50 3 7 0 AD8041 2 4 8 6 -10 G = +2 -20 330 330 -30 -40 F1 = 4.9MHz FUNDAMENTAL = 0.6dB SECOND HARMONIC = 66.9dB THIRD HARMONIC = 74.7dB SNR = 55.2dB NOISE FLOOR = - 86.1dB ENCODE FREQUENCY = 40MHz 13 12 11 10 -50 -60 -70 -80 -90 -100 74HC04 Figure 7. 2:1 Multiplexer Figure 10. FFT Output of Circuit in Figure 9 -12- REV. B AD8041 APPLICATIONS RGB Buffer Single-Supply Composite Video Line Driver The AD8041 can provide buffering of RGB signals that include ground while operating from a single 3 V or 5 V supply. The signals that drive an RGB monitor are usually supplied by current output DACs that operate from a 5 V only supply. These can triple DACs like the ADV7120 and ADV7122 from Analog Devices or integrate into the graphics controller IC as in most PCs these days. During the horizontal blanking interval, the currents output from the DACs go to zero and the RGB signals are pulled to ground via the termination resistors. If more than one RGB monitor is desired, it cannot simply be connected in parallel because it will provide an additional termination. Therefore, buffering must be provided before connecting a second monitor. Since the RGB signals include ground as part of their dynamic output range, it has previously been required to use a dualsupply op amp to provide this buffering. In some systems, this is the only component that requires a negative supply, so it can be quite inconvenient to incorporate this multiple monitor feature. Figure 11 shows a schematic of one channel of a single-supply, gain-of-two buffer for driving a second RGB monitor. No current is required when the amplifier output is at ground. The termination resistor at the monitor helps pull the output down at low voltage levels. 3V OR 5V Figure 13 shows a schematic of a single-supply gain-of-two composite video line driver. Since the sync tips of a composite video signal extend below ground, the input must be ac-coupled and shifted positively to provide signal swing during these negative excursions in a single-supply configuration. The input is terminated in 75 and ac-coupled via CIN to a voltage divider that provides the dc bias point to the input. Setting the optimal bias point requires some understanding of the nature of composite video signals and the video performance of the AD8041. Signals of bounded peak-to-peak amplitude that vary in duty cycle require larger dynamic swing capability than their peak-topeak amplitude after ac coupling. As a worst case, the dynamic signal swing required will approach twice the peak-to-peak value. The two bounding cases are for a duty cycle that is mostly low, but occasionally goes high at a fraction of a percent duty cycle and vice versa. Composite video is not quite this demanding. One bounding extreme is for a signal that is mostly black for an entire frame but has a white (full intensity), minimum width spike at least once per frame. The other extreme is for a video signal that is full white everywhere. The blanking intervals and sync tips of such a signal will have negative going excursions in compliance with composite video specifications. The combination of horizontal and vertical blanking intervals limit such a signal to being at its highest level (white) for only about 75% of the time. As a result of the duty cycle variations between the two extremes presented above, a 1 V p-p composite video signal that is multiplied by a gain of two requires about 3.2 V p-p of dynamic voltage swing at the output for an op amp to pass a composite video signal of arbitrary duty cycle without distortion. Some circuits use a sync tip clamp along with ac coupling to hold the sync tips at a relatively constant level in order to lower the amount of dynamic signal swing required. However, these circuits can have artifacts like sync tip compression unless they are driven by sources with very low output impedance. 5V 4.99k 4.99k 47 F COMPOSITE VIDEO IN 75 10k 2 3 7 1000 F 10 F 0.1 F 0.1 F NC R, G OR B 3 7 8 75 6 4 1k 1k PRIMARY RGB MONITOR 10 F AD8041 2 75 75 SECOND RGB MONITOR Figure 11. Single-Supply RGB Buffer Figure 12 is an oscilloscope photo of the circuit in Figure 11 operating from a 3 V supply and driven by the blue signal of a color bar pattern. Note that the input and output are at ground during the horizontal blanking interval. The RGB signals are specified to output a maximum of 700 mV peak. The output of the AD8041 is 1.4 V with the termination resistors providing a divide-by-two. The red and green signals can be buffered in the same manner with duplication of this circuit. 500mV VIN 100 90 10 F 75 COAX RT 75 0.1 F AD8041 8 4 NC 6 VOUT RL 75 5s RG 1k 220 F GND RF 1k Figure 13. Single-Supply Composite Video Line Driver VOUT 10 0% GND 500mV Figure 12. 3 V, RGB Buffer The AD8041 not only has ample signal swing capability to handle the dynamic range required without using a sync tip clamp but also has good video specifications like differential gain and differential phase when buffering these signals in an accoupled configuration. REV. B -13- AD8041 To test this, the differential gain and differential phase were measured for the AD8041 while the supplies were varied. As the lower supply is raised to approach the video signal, the first effect to be observed is that the sync tips become compressed before the differential gain and differential phase are adversely affected. Thus, there must be adequate swing in the negative direction to pass the sync tips without compression. As the upper supply is lowered to approach the video, the differential gain and differential phase were not significantly adversely affected until the difference between the peak video output and the supply reached 0.6 V. Thus, the highest video level should be kept at least 0.6 V below the positive supply rail. Taking the above into account, it was found that the optimal point to bias the noninverting input is at 2.2 V dc. Operating at this point, the worst-case differential gain is measured at 0.06% and the worst-case differential phase is 0.06. The ac coupling capacitors used in the circuit at first glance appear quite large. A composite video signal has a lower frequency band edge of 30 Hz. The resistances at the various ac coupling points--especially at the output--are quite small. In order to minimize phase shifts and baseline tilt, the large value capacitors are required. For video system performance that is not to be of the highest quality, the value of these capacitors can be reduced by a factor of up to five with only a slightly observable change in the picture quality. Sync Stripper Referring to Figure 15, the green plus sync signal is output from an ADV7120, a single-supply triple video DAC. Because the DAC is single supply, the lowest level of the sync tip is at ground or slightly above. The AD8041 is set for a gain of two to compensate for the divide by two of the output terminations. 500mV 100 90 10 s 10 0% 500mV Figure 15. Single-Supply Sync Stripper The reference voltage for R1 should be twice the dc blanking level of the G signal. If the blanking level is at ground and the sync tip is negative as in some dual-supply systems, then R1 can be tied to ground. In either case, the output will have the sync removed and have the blanking level at ground. Layout Considerations Some RGB monitor systems use only three cables total and carry the synchronizing signals along with the green (G) signal on the same cable. The sync signals are pulses that go in the negative direction from the blanking level of the G signal. In some applications like prior to digitizing component video signals with A/D converters, it is desirable to remove or strip the sync portion from the G signal. Figure 14 is a schematic of a circuit using the AD8041 running on a single 5 V supply that performs this function. GREEN W/SYNC GREEN W/OUT SYNC The specified high speed performance of the AD8041 requires careful attention to board layout and component selection. Proper RF design techniques and low-pass parasitic component selection are necessary. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the area near the input pins to reduce the stray capacitance. Chip capacitors should be used for the supply bypassing. One end should be connected to the ground plane and the other within 1/8 inch of each power pin. An additional large (0.47 F to 10 F) tantalum electrolytic capacitor should be connected in parallel, but not necessarily so close, to supply current for fast, large signal changes at the output. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high speed performance. Stripline design techniques should be used for long signal traces (greater than about 1 inch). These should be designed with a characteristic impedance of 50 or 75 and be properly terminated at each end. VBLANK +0.4 GROUND 5V 0.1 F 7 GROUND 10 F VIN 75 3 75 AD8041 2 4 6 75 (MONITOR) R1 1k R2 1k 0.8V (2X VBLANK) Figure 14. Single-Supply Sync Stripper -14- REV. B AD8041 OUTLINE DIMENSIONS 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 8 5 8-Lead Standard Small Outline Package [SOIC] (R-8) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 8 5 4 1 4 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) MIN SEATING PLANE 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 5.80 (0.2284) 0.100 (2.54) BSC 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE 1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.17 (0.0067) 0.50 (0.0196) 0.25 (0.0099) 45 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.51 (0.0201) 0.31 (0.0122) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) 0.005 (0.13) MIN 8 0.055 (1.40) MAX 5 PIN 1 1 4 0.310 (7.87) 0.220 (5.59) 0.100 (2.54) BSC 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15 0 0.015 (0.38) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. B -15- AD8041 Revision History Location 5/03--Data Sheet changed from REV. A to REV. B. Page Deleted all references to evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal 4/01--Data Sheet changed from REV. 0 to REV. A. C01058-0-6/03(B) Updated OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Specifications changed DISABLE CHARACTERISTICS, Off Voltage (Device Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -16- REV. B |
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